Product Summary

The EPM7128SQC100-15N is a high-density, high-performance PLD, which is based on the second-generation MAX architecture of Altera. Fabricated with advanced CMOS technology, the EPM7128SQC100-15N provides 600 to 5,000 usable gates, ISP, pin-to-pin delays as fast as 5 ns, and counter speeds of up to 175.4 MHz.

Parametrics

EPM7128SQC100-15N maximum ratings: (1)Supply voltage With respect to ground (2): –2.0 to 7.0 V; (2)DC input voltage: –2.0 to 7.0 V; (3)DC output current, per pin: –25 to 25 mA; (4)Storage temperature No bias –65 150℃; (5)Ambient temperature Under bias: –65 to 135℃; (6)Junction temperature: Ceramic packages, under bias, 150℃; (7)PQFP and RQFP packages, under bias 135 ℃.

Features

EPM7128SQC100-15N features: (1)Open-drain output option in MAX 7000S devices; (2)Programmable macrocell flipflops with individual clear, preset; (3)clock, and clock enable controls; (4)Programmable power-saving mode for a reduction of over 50% in each macrocell; (5)Configurable expander product-term distribution, allowing up to 32 product terms per macrocell; (6)Programmable security bit for protection of proprietary designs; (7)3.3-V or 5.0-V operation.

Diagrams

EPM7128SQC100-15N circuit diagram

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